Recent developments in semiconductor technology enable semiconductor devices with reduced size gate electrodes to be obtained, which results in an increase in digital calculation speed. Semiconductor devices are increasingly used in analog circuits, such as power supply circuits, as well as in digital circuits.
Characteristics of an analog circuit having semiconductor devices are significantly affected by variations in physical properties of the semiconductor devices, such as resistance, capacitance, and dependence on temperature and voltage.
In particular, variations in temperature dependence of semiconductor devices used in circuitry may cause undesired effects on the circuitry, which are typically negligible for a digital circuit, but cannot be ignored for an analog circuit.
Thus, temperature dependence of semiconductor devices in analog circuitry needs to be leveled.
An approach to reduce the variations in temperature dependence is to design the analog circuitry so that temperature coefficients of semiconductor devices cancel each other out.
Referring to FIG. 1, a diagram showing a constant current circuit 90′ including semiconductor devices of different temperature dependence is described.
In FIG. 1, the constant current circuit 90′ includes a power supply terminal 38, an operational amplifier 44 (hereinafter referred to as “op-amp 44”), metal-oxide semiconductor (MOS) transistors M1, M2, and M3, bipolar transistors Q1 and Q2, and a resistor X1.
The MOS transistors M1 through M3 have identical characteristics, and are connected as a current mirror. The MOS transistors M1 through M3 have sources connected to a supply circuit (not shown) via the power supply terminal 38.
The MOS transistor M1 is grounded via the bipolar transistor Q1. The MOS transistor M2 is grounded via the resistor X1 and the bipolar transistor Q2.
The bipolar transistors Q1 and Q2 are basically identical in characteristics, except for different base-emitter junction areas. The ratio of the base-emitter junction area of the bipolar transistor Q1 to that of Q2 is defined as 1:n (n>1). Each of the MOS transistors Q1 and Q2 has a base and a collector grounded.
The op-amp 44 has a negative, inverting input terminal and a positive, non-inverting input terminal. The inverting input terminal receives an input of electric potential derived from a base-emitter voltage VBE1 of the bipolar transistor Q1. The non-inverting input terminal receives an input of electric potential derived from a base-emitter voltage VBE2 of the bipolar transistor Q2 and a voltage ΔVBE applied across the resistor X′.
In the constant current circuit 90′, negative feedback is applied so that the input voltage to the non-inverting input terminal and the input voltage to the inverting input terminal are substantially equal. Due to the negative feedback, the voltage ΔVBE has a potential substantially equal to a difference between the base-emitter voltage VBE1 and the base-emitter voltage VBE2.
The MOS transistors M1 through M3 have a common drain current substantially equal to a reference current I. The bipolar transistor Q2 has a saturation current Is2 which is n times as large as a saturation current Is1 of the bipolar transistor Q1. Each of the bipolar transistors Q1 and Q2 has an emitter biased with a common current I0.
Consequently, the voltage ΔVBE applied across the resistor X′ is represented by the following equation:
                                                                        Δ                ⁢                                                                  ⁢                                  V                  BE                                            =                                                V                                      BE                    ⁢                                                                                  ⁢                    1                                                  -                                  V                                      BE                    ⁢                                                                                  ⁢                    2                                                                                                                          =                                                                    V                    t                                    *                                      ln                    ⁡                                          (                                                                        I                          0                                                /                                                  I                                                      s                            ⁢                                                                                                                  ⁢                            1                                                                                              )                                                                      -                                                      V                    t                                    *                                      ln                    ⁡                                          (                                                                        I                          0                                                /                                                  I                                                      s                            ⁢                                                                                                                  ⁢                            2                                                                                              )                                                                                                                                                              =                                                      V                    t                                    *                                      ln                    ⁡                                          (                      n                      )                                                                                  ,                                                          Equation        ⁢                                  [        1        ]            
where Vt is thermal voltage given by kT/q with absolute temperature T (K), Boltzmann constant k=1.38*10−13 (J/K), and elementary charge q=1.6*10−19 (C).
As the right-hand side of the Equation [1] is equal to I*R with R denoting the resistance of the resistor X′, the reference current I is represented as Vt*ln(n)/R. Consequently, the temperature coefficient TC(I) of the reference current I is represented by the following equation:
                                                                        TC                ⁡                                  (                  I                  )                                            =                                                1                  /                  I                                *                                                      ∂                    I                                    /                                      ∂                    T                                                                                                                          =                                                TC                  ⁡                                      (                                          V                      t                                        )                                                  +                                  TC                  ⁡                                      (                                          1                      /                      R                                        )                                                                                                                          =                                                TC                  ⁡                                      (                                          V                      t                                        )                                                  -                                                      TC                    ⁡                                          (                      R                      )                                                        .                                                                                        Equation        ⁢                                  [        2        ]            
Given that the reference temperature T=300 (K), the value of TC(Vt) is 3333 ppm/° C. According to Equation [2], the temperature coefficient TC(I) of the reference current I can be reduced to 0 by adjusting the temperature coefficient TC(R) of the resistor X′ to be 3333 ppm/° C.
The temperature coefficient TC(R) of the resistor X′ is given by the following equation:TC(R)=(RT−RRT)/RRT  Equation [3],
where RT represents a resistance value at the reference temperature T and RRT represents a resistance value at room temperature, i.e., 25° C.
The resistor X′ in the constant current circuit 90′ may be configured as a semiconductor device having N-well and/or P-well regions.
Referring to FIGS. 2A and 2B, a schematic illustration of a background art semiconductor device 100 is described. FIG. 2A shows a plan view of the semiconductor device 100. FIG. 2B shows a cross-sectional view of the semiconductor device 100 taken along line F-F of FIG. 2A.
The semiconductor device 100 includes a substrate 102, a pair of side portions 103a and 103b, an N-well 104, and an isolation layer 112.
Each of the side portions 103a and 103b includes a contact region 106, a silicide layer 108, and a pair of contacts 110a and 110b. 
The N-well 104 is formed at a main surface of the substrate 102. The contact region 106 is an N+ region, disposed substantially at each end of the N-well 104. The silicide layer 108 is disposed on the contact region 106. The pair of contacts 110a and 110b are formed on the silicide layer 108.
The semiconductor device 100 has a shallow trench isolation (STI) structure. The N-well 104 is electrically isolated by the isolation layer 112 formed of silicon dioxide, which is deposited over the N-well 104 and the substrate 102 except for areas corresponding to the contact region 106.
In the semiconductor device 100, the N-well 104 exhibits a resistance which can be controlled by varying the size of the N-well 104.
For example, in prototype testing stage for the semiconductor device 100, the size of the N-well 104 is varied by altering the length and width of the N-well 104.
As the manufacture of the semiconductor device 100 involves lithography processes, in which the N-well 104 and other components, such as the contact region 106 and the pair of contacts 110a and 110b, are formed using photoresist masks, altering the length and width of the N-well 104 results in a need to replace patterns of the photoresist masks for the N-well 104 as well as other neighboring components.
The resistance of the N-well 104 can also be controlled by varying the depth of the N-well 104. In a background art fabrication process, the resistance of the N-well 104 is reduced by forming the isolation layer 112 so that the N-well 104 has a relatively large depth. Such a process is effective in reducing a substrate bias, but does not provide a solution to control the temperature dependence of the resistance.
To control the temperature dependence of resistance of the semiconductor device 100, a method has been proposed in which the thermal property of the resistance derived from the N-well 104 is corrected by introducing another resistive element of different thermal property. However, accurate control of the temperature dependence of resistance is difficult due to variations in producing the different types of resistive elements.